`timescale 1ns / 1ps

`include "soc_define.sv"

module asic_system ();
  localparam OSC_CLK_25M_PEROID = 40;
  localparam OSC_CLK_12288K_PEROID = 81.38;

  wire                                    osc_clk_25m_i_pad;
  wire                                    osc_clk_12288k_i_pad;
  wire                                    ext_rst_n_i_pad;
  wire                                    uart0_uart_rx_i_pad;
  wire                                    uart0_uart_tx_o_pad;
  wire                                    tmr0_capch_i_pad;
  wire                                    tmr1_capch_i_pad;
  wire                                    tmr2_capch_i_pad;
  wire                                    tmr3_capch_i_pad;
  wire                                    i2c0_scl_io_pad;
  wire                                    i2c0_sda_io_pad;
  wire                                    spi0_spi_sck_o_pad;
  wire                                    spi0_spi_nss_o_pad;
  wire                                    spi0_spi_io_pad0;
  wire                                    spi0_spi_io_pad1;
  wire                                    spi0_spi_io_pad2;
  wire                                    spi0_spi_io_pad3;
  wire                                    spi1_spi_sck_o_pad;
  wire                                    spi1_spi_nss_o_pad;
  wire                                    spi1_spi_io_pad0;
  wire                                    spi1_spi_io_pad1;
  wire                                    spi1_spi_io_pad2;
  wire                                    spi1_spi_io_pad3;
  wire                                    ps20_ps2_clk_i_pad;
  wire                                    ps20_ps2_dat_i_pad;
  wire                                    rcu0_pll_en_i_pad;
  wire [                             2:0] rcu0_clk_cfg_i_pad;
  wire                                    old_ip_spi_flash_clk_o_pad;
  wire                                    old_ip_spi_flash_cs_o_pad0;
  wire                                    old_ip_spi_flash_cs_o_pad1;
  wire                                    old_ip_spi_flash_mosi_o_pad;
  wire                                    old_ip_spi_flash_miso_i_pad;
  wire                                    old_ip_uart_rx_i_pad;
  wire                                    old_ip_uart_tx_o_pad;
  wire                                    old_ip_chiplink_rx_clk_i_pad;
  wire                                    old_ip_chiplink_rx_rst_i_pad;
  wire                                    old_ip_chiplink_rx_send_i_pad;
  wire                                    old_ip_chiplink_rx_send_i_pad_dely;
  wire [`SOCDF_CPLINK_DATA_WIDTH - 1 : 0] old_ip_chiplink_rx_data_i_pad;
  wire [`SOCDF_CPLINK_DATA_WIDTH - 1 : 0] old_ip_chiplink_rx_data_i_pad_dely;
  wire                                    old_ip_chiplink_tx_clk_o_pad;
  wire                                    old_ip_chiplink_tx_rst_o_pad;
  wire                                    old_ip_chiplink_tx_send_o_pad;
  wire [`SOCDF_CPLINK_DATA_WIDTH - 1 : 0] old_ip_chiplink_tx_data_o_pad;
  wire                                    old_ip_sdram_clk_o_pad;
  wire                                    old_ip_sdram_cke_o_pad;
  wire                                    old_ip_sdram_cs_o_pad;
  wire                                    old_ip_sdram_ras_o_pad;
  wire                                    old_ip_sdram_cas_o_pad;
  wire                                    old_ip_sdram_we_o_pad;
  wire [                             1:0] old_ip_sdram_dqm_o_pad;
  wire [                            12:0] old_ip_sdram_addr_o_pad;
  wire [                             1:0] old_ip_sdram_ba_o_pad;
  wire [                            15:0] old_ip_sdram_data_io_pad;

  logic osc_clk_25m_i, osc_clk_12288k_i, ext_rst_n_i, rcu0_pll_en_i;
  logic [2:0] rcu0_clk_cfg_i;

  assign    osc_clk_25m_i_pad                  = osc_clk_25m_i;
  assign    osc_clk_12288k_i_pad               = osc_clk_12288k_i;
  assign    ext_rst_n_i_pad                    = ext_rst_n_i;
  assign    rcu0_pll_en_i_pad                  = rcu0_pll_en_i;
  assign    rcu0_clk_cfg_i_pad                 = rcu0_clk_cfg_i;
  // chiplink
  assign #1 old_ip_chiplink_rx_send_i_pad_dely = old_ip_chiplink_rx_send_i_pad;
  assign #1 old_ip_chiplink_rx_data_i_pad_dely = old_ip_chiplink_rx_data_i_pad;

  task sim_reset(int delay);
    ext_rst_n_i = 1'b0;
    repeat (delay) @(posedge osc_clk_25m_i_pad);
    #1 ext_rst_n_i = 1'b1;
  endtask

  asic_top u_asic_top (
      .osc_clk_25m_i_pad             (osc_clk_25m_i_pad),
      .osc_clk_25m_o_pad             (),
      .osc_clk_12288k_i_pad          (osc_clk_12288k_i_pad),
      .osc_clk_12288k_o_pad          (),
      .ext_rst_n_i_pad               (ext_rst_n_i_pad),
      .uart0_uart_rx_i_pad           (uart0_uart_rx_i_pad),
      .uart0_uart_tx_o_pad           (uart0_uart_tx_o_pad),
      .gpio0_gpio_io_pad0            (),
      .gpio0_gpio_io_pad1            (),
      .gpio0_gpio_io_pad2            (),
      .gpio0_gpio_io_pad3            (),
      .gpio0_gpio_io_pad4            (),
      .gpio0_gpio_io_pad5            (),
      .gpio0_gpio_io_pad6            (),
      .gpio0_gpio_io_pad7            (),
      .pwm0_pwm_o_pad0               (),
      .pwm0_pwm_o_pad1               (),
      .pwm0_pwm_o_pad2               (),
      .pwm0_pwm_o_pad3               (),
      .pwm1_pwm_o_pad0               (),
      .pwm1_pwm_o_pad1               (),
      .pwm1_pwm_o_pad2               (),
      .pwm1_pwm_o_pad3               (),
      .pwm2_pwm_o_pad0               (),
      .pwm2_pwm_o_pad1               (),
      .pwm2_pwm_o_pad2               (),
      .pwm2_pwm_o_pad3               (),
      .tmr0_capch_i_pad              (tmr0_capch_i_pad),
      .tmr1_capch_i_pad              (tmr1_capch_i_pad),
      .tmr2_capch_i_pad              (tmr2_capch_i_pad),
      .tmr3_capch_i_pad              (tmr3_capch_i_pad),
      .i2c0_scl_io_pad               (i2c0_scl_io_pad),
      .i2c0_sda_io_pad               (i2c0_sda_io_pad),
      .spi0_spi_sck_o_pad            (spi0_spi_sck_o_pad),
      .spi0_spi_nss_o_pad            (spi0_spi_nss_o_pad),
      .spi0_spi_io_pad0              (spi0_spi_io_pad0),
      .spi0_spi_io_pad1              (spi0_spi_io_pad1),
      .spi0_spi_io_pad2              (spi0_spi_io_pad2),
      .spi0_spi_io_pad3              (spi0_spi_io_pad3),
      .spi1_spi_sck_o_pad            (spi1_spi_sck_o_pad),
      .spi1_spi_nss_o_pad            (spi1_spi_nss_o_pad),
      .spi1_spi_io_pad0              (spi1_spi_io_pad0),
      .spi1_spi_io_pad1              (spi1_spi_io_pad1),
      .spi1_spi_io_pad2              (spi1_spi_io_pad2),
      .spi1_spi_io_pad3              (spi1_spi_io_pad3),
      .vgalcd0_vgalcd_r_o_pad0       (),
      .vgalcd0_vgalcd_r_o_pad1       (),
      .vgalcd0_vgalcd_r_o_pad2       (),
      .vgalcd0_vgalcd_r_o_pad3       (),
      .vgalcd0_vgalcd_r_o_pad4       (),
      .vgalcd0_vgalcd_g_o_pad0       (),
      .vgalcd0_vgalcd_g_o_pad1       (),
      .vgalcd0_vgalcd_g_o_pad2       (),
      .vgalcd0_vgalcd_g_o_pad3       (),
      .vgalcd0_vgalcd_g_o_pad4       (),
      .vgalcd0_vgalcd_g_o_pad5       (),
      .vgalcd0_vgalcd_b_o_pad0       (),
      .vgalcd0_vgalcd_b_o_pad1       (),
      .vgalcd0_vgalcd_b_o_pad2       (),
      .vgalcd0_vgalcd_b_o_pad3       (),
      .vgalcd0_vgalcd_b_o_pad4       (),
      .vgalcd0_vgalcd_hsync_o_pad    (),
      .vgalcd0_vgalcd_vsync_o_pad    (),
      .vgalcd0_vgalcd_de_o_pad       (),
      .vgalcd0_vgalcd_pclk_o_pad     (),
      .ps20_ps2_clk_i_pad            (ps20_ps2_clk_i_pad),
      .ps20_ps2_dat_i_pad            (ps20_ps2_dat_i_pad),
      .rcu0_pll_en_i_pad             (rcu0_pll_en_i_pad),
      .rcu0_clk_cfg_i_pad0           (rcu0_clk_cfg_i_pad[0]),
      .rcu0_clk_cfg_i_pad1           (rcu0_clk_cfg_i_pad[1]),
      .rcu0_clk_cfg_i_pad2           (rcu0_clk_cfg_i_pad[2]),
      .old_ip_spi_flash_clk_o_pad    (old_ip_spi_flash_clk_o_pad),
      .old_ip_spi_flash_cs_o_pad0    (old_ip_spi_flash_cs_o_pad0),
      .old_ip_spi_flash_cs_o_pad1    (old_ip_spi_flash_cs_o_pad1),
      .old_ip_spi_flash_mosi_o_pad   (old_ip_spi_flash_mosi_o_pad),
      .old_ip_spi_flash_miso_i_pad   (old_ip_spi_flash_miso_i_pad),
      .old_ip_uart_rx_i_pad          (old_ip_uart_rx_i_pad),
      .old_ip_uart_tx_o_pad          (old_ip_uart_tx_o_pad),
      .old_ip_chiplink_rx_clk_i_pad  (old_ip_chiplink_rx_clk_i_pad),
      .old_ip_chiplink_rx_rst_i_pad  (old_ip_chiplink_rx_rst_i_pad),
      .old_ip_chiplink_rx_send_i_pad (old_ip_chiplink_rx_send_i_pad_dely),
      .old_ip_chiplink_rx_data_i_pad0(old_ip_chiplink_rx_data_i_pad_dely[0]),
      .old_ip_chiplink_rx_data_i_pad1(old_ip_chiplink_rx_data_i_pad_dely[1]),
      .old_ip_chiplink_rx_data_i_pad2(old_ip_chiplink_rx_data_i_pad_dely[2]),
      .old_ip_chiplink_rx_data_i_pad3(old_ip_chiplink_rx_data_i_pad_dely[3]),
      .old_ip_chiplink_rx_data_i_pad4(old_ip_chiplink_rx_data_i_pad_dely[4]),
      .old_ip_chiplink_rx_data_i_pad5(old_ip_chiplink_rx_data_i_pad_dely[5]),
      .old_ip_chiplink_rx_data_i_pad6(old_ip_chiplink_rx_data_i_pad_dely[6]),
      .old_ip_chiplink_rx_data_i_pad7(old_ip_chiplink_rx_data_i_pad_dely[7]),
      .old_ip_chiplink_tx_clk_o_pad  (old_ip_chiplink_tx_clk_o_pad),
      .old_ip_chiplink_tx_rst_o_pad  (old_ip_chiplink_tx_rst_o_pad),
      .old_ip_chiplink_tx_send_o_pad (old_ip_chiplink_tx_send_o_pad),
      .old_ip_chiplink_tx_data_o_pad0(old_ip_chiplink_tx_data_o_pad[0]),
      .old_ip_chiplink_tx_data_o_pad1(old_ip_chiplink_tx_data_o_pad[1]),
      .old_ip_chiplink_tx_data_o_pad2(old_ip_chiplink_tx_data_o_pad[2]),
      .old_ip_chiplink_tx_data_o_pad3(old_ip_chiplink_tx_data_o_pad[3]),
      .old_ip_chiplink_tx_data_o_pad4(old_ip_chiplink_tx_data_o_pad[4]),
      .old_ip_chiplink_tx_data_o_pad5(old_ip_chiplink_tx_data_o_pad[5]),
      .old_ip_chiplink_tx_data_o_pad6(old_ip_chiplink_tx_data_o_pad[6]),
      .old_ip_chiplink_tx_data_o_pad7(old_ip_chiplink_tx_data_o_pad[7]),
      .old_ip_sdram_clk_o_pad        (old_ip_sdram_clk_o_pad),
      .old_ip_sdram_cke_o_pad        (old_ip_sdram_cke_o_pad),
      .old_ip_sdram_cs_o_pad         (old_ip_sdram_cs_o_pad),
      .old_ip_sdram_ras_o_pad        (old_ip_sdram_ras_o_pad),
      .old_ip_sdram_cas_o_pad        (old_ip_sdram_cas_o_pad),
      .old_ip_sdram_we_o_pad         (old_ip_sdram_we_o_pad),
      .old_ip_sdram_dqm_o_pad0       (old_ip_sdram_dqm_o_pad[0]),
      .old_ip_sdram_dqm_o_pad1       (old_ip_sdram_dqm_o_pad[1]),
      .old_ip_sdram_addr_o_pad0      (old_ip_sdram_addr_o_pad[0]),
      .old_ip_sdram_addr_o_pad1      (old_ip_sdram_addr_o_pad[1]),
      .old_ip_sdram_addr_o_pad2      (old_ip_sdram_addr_o_pad[2]),
      .old_ip_sdram_addr_o_pad3      (old_ip_sdram_addr_o_pad[3]),
      .old_ip_sdram_addr_o_pad4      (old_ip_sdram_addr_o_pad[4]),
      .old_ip_sdram_addr_o_pad5      (old_ip_sdram_addr_o_pad[5]),
      .old_ip_sdram_addr_o_pad6      (old_ip_sdram_addr_o_pad[6]),
      .old_ip_sdram_addr_o_pad7      (old_ip_sdram_addr_o_pad[7]),
      .old_ip_sdram_addr_o_pad8      (old_ip_sdram_addr_o_pad[8]),
      .old_ip_sdram_addr_o_pad9      (old_ip_sdram_addr_o_pad[9]),
      .old_ip_sdram_addr_o_pad10     (old_ip_sdram_addr_o_pad[10]),
      .old_ip_sdram_addr_o_pad11     (old_ip_sdram_addr_o_pad[11]),
      .old_ip_sdram_addr_o_pad12     (old_ip_sdram_addr_o_pad[12]),
      .old_ip_sdram_ba_o_pad0        (old_ip_sdram_ba_o_pad[0]),
      .old_ip_sdram_ba_o_pad1        (old_ip_sdram_ba_o_pad[1]),
      .old_ip_sdram_data_io_pad0     (old_ip_sdram_data_io_pad[0]),
      .old_ip_sdram_data_io_pad1     (old_ip_sdram_data_io_pad[1]),
      .old_ip_sdram_data_io_pad2     (old_ip_sdram_data_io_pad[2]),
      .old_ip_sdram_data_io_pad3     (old_ip_sdram_data_io_pad[3]),
      .old_ip_sdram_data_io_pad4     (old_ip_sdram_data_io_pad[4]),
      .old_ip_sdram_data_io_pad5     (old_ip_sdram_data_io_pad[5]),
      .old_ip_sdram_data_io_pad6     (old_ip_sdram_data_io_pad[6]),
      .old_ip_sdram_data_io_pad7     (old_ip_sdram_data_io_pad[7]),
      .old_ip_sdram_data_io_pad8     (old_ip_sdram_data_io_pad[8]),
      .old_ip_sdram_data_io_pad9     (old_ip_sdram_data_io_pad[9]),
      .old_ip_sdram_data_io_pad10    (old_ip_sdram_data_io_pad[10]),
      .old_ip_sdram_data_io_pad11    (old_ip_sdram_data_io_pad[11]),
      .old_ip_sdram_data_io_pad12    (old_ip_sdram_data_io_pad[12]),
      .old_ip_sdram_data_io_pad13    (old_ip_sdram_data_io_pad[13]),
      .old_ip_sdram_data_io_pad14    (old_ip_sdram_data_io_pad[14]),
      .old_ip_sdram_data_io_pad15    (old_ip_sdram_data_io_pad[15])
  );

  wire        io_axi4_0_awready;
  wire        io_axi4_0_awvalid;
  wire [ 3:0] io_axi4_0_awid;
  wire [31:0] io_axi4_0_awaddr;
  wire [ 7:0] io_axi4_0_awlen;
  wire [ 2:0] io_axi4_0_awsize;
  wire [ 1:0] io_axi4_0_awburst;
  wire        io_axi4_0_wready;
  wire        io_axi4_0_wvalid;
  wire [63:0] io_axi4_0_wdata;
  wire [ 7:0] io_axi4_0_wstrb;
  wire        io_axi4_0_wlast;
  wire        io_axi4_0_bready;
  wire        io_axi4_0_bvalid;
  wire [ 3:0] io_axi4_0_bid;
  wire [ 1:0] io_axi4_0_bresp;
  wire        io_axi4_0_arready;
  wire        io_axi4_0_arvalid;
  wire [ 3:0] io_axi4_0_arid;
  wire [31:0] io_axi4_0_araddr;
  wire [ 7:0] io_axi4_0_arlen;
  wire [ 2:0] io_axi4_0_arsize;
  wire [ 1:0] io_axi4_0_arburst;
  wire        io_axi4_0_rready;
  wire        io_axi4_0_rvalid;
  wire [ 3:0] io_axi4_0_rid;
  wire [63:0] io_axi4_0_rdata;
  wire [ 1:0] io_axi4_0_rresp;
  wire        io_axi4_0_rlast;

  wire        mmio_axi4_0_awready;
  wire        mmio_axi4_0_awvalid;
  wire [ 3:0] mmio_axi4_0_awid;
  wire [30:0] mmio_axi4_0_awaddr;
  wire [ 7:0] mmio_axi4_0_awlen;
  wire [ 2:0] mmio_axi4_0_awsize;
  wire [ 1:0] mmio_axi4_0_awburst;
  wire        mmio_axi4_0_wready;
  wire        mmio_axi4_0_wvalid;
  wire [63:0] mmio_axi4_0_wdata;
  wire [ 7:0] mmio_axi4_0_wstrb;
  wire        mmio_axi4_0_wlast;
  wire        mmio_axi4_0_bready;
  wire        mmio_axi4_0_bvalid;
  wire [ 3:0] mmio_axi4_0_bid;
  wire [ 1:0] mmio_axi4_0_bresp;
  wire        mmio_axi4_0_arready;
  wire        mmio_axi4_0_arvalid;
  wire [ 3:0] mmio_axi4_0_arid;
  wire [30:0] mmio_axi4_0_araddr;
  wire [ 7:0] mmio_axi4_0_arlen;
  wire [ 2:0] mmio_axi4_0_arsize;
  wire [ 1:0] mmio_axi4_0_arburst;
  wire        mmio_axi4_0_rready;
  wire        mmio_axi4_0_rvalid;
  wire [63:0] mmio_axi4_0_rdata;
  wire [ 1:0] mmio_axi4_0_rresp;
  wire        mmio_axi4_0_rlast;


  rs232 #(115200, 0) u_uart0_rs232 (
      .rs232_rx_i(uart0_uart_tx_o_pad),
      .rs232_tx_o(uart0_uart_rx_i_pad)
  );

  pullup (i2c0_scl_io_pad);
  pullup (i2c0_sda_io_pad);
  AT24C04 u_i2c0_AT24C04 (
      .WP (1'b0),
      .SCL(i2c0_scl_io_pad),
      .SDA(i2c0_sda_io_pad)
  );

  W25Q128JVxIM u_spi0_W25Q128JVxIM (
      .CSn  (spi0_spi_nss_o_pad),
      .CLK  (spi0_spi_sck_o_pad),
      .DIO  (spi0_spi_io_pad0),
      .DO   (spi0_spi_io_pad1),
      .WPn  (spi0_spi_io_pad2),
      .HOLDn(spi0_spi_io_pad3)
  );

  W25Q128JVxIM u_spi1_W25Q128JVxIM (
      .CSn  (spi1_spi_nss_o_pad),
      .CLK  (spi1_spi_sck_o_pad),
      .DIO  (spi1_spi_io_pad0),
      .DO   (spi1_spi_io_pad1),
      .WPn  (spi1_spi_io_pad2),
      .HOLDn(spi1_spi_io_pad3)
  );

  kdb_model u_ps20_kdb_model (
      .ps2_clk_o(ps20_ps2_clk_i_pad),
      .ps2_dat_o(ps20_ps2_dat_i_pad)
  );

  N25Qxxx u_old_ip_spi_N25Qxxx (
      .C_       (old_ip_spi_flash_clk_o_pad),
      .S        (old_ip_spi_flash_cs_o_pad0),
      .DQ0      (old_ip_spi_flash_mosi_o_pad),
      .DQ1      (old_ip_spi_flash_miso_i_pad),
      .HOLD_DQ3 (),
      .Vpp_W_DQ2(),
      .Vcc      ('d3000)
  );

  tty #(115200, 0) u_old_ip_uart_tty (
      .STX(old_ip_uart_rx_i_pad),
      .SRX(old_ip_uart_tx_o_pad)
  );

  //chiplink sim connect to dual chiplink
  FPGA_ChiplinkBridge u_old_ip_chiplink_FPGA_ChiplinkBridge (
      .clock                   (osc_clk_25m_i_pad),
      .reset                   (~ext_rst_n_i_pad),               // sync to osc_clk_25m_i_pad
      .fpga_io_c2b_clk         (old_ip_chiplink_rx_clk_i_pad),
      .fpga_io_c2b_rst         (old_ip_chiplink_rx_rst_i_pad),
      .fpga_io_c2b_send        (old_ip_chiplink_rx_send_i_pad),
      .fpga_io_c2b_data        (old_ip_chiplink_rx_data_i_pad),
      .fpga_io_b2c_clk         (old_ip_chiplink_tx_clk_o_pad),
      .fpga_io_b2c_rst         (old_ip_chiplink_tx_rst_o_pad),
      .fpga_io_b2c_send        (old_ip_chiplink_tx_send_o_pad),
      .fpga_io_b2c_data        (old_ip_chiplink_tx_data_o_pad),
      //mem
      .mem_axi4_0_awready      (io_axi4_0_awready),
      .mem_axi4_0_awvalid      (io_axi4_0_awvalid),
      .mem_axi4_0_awid         (io_axi4_0_awid),
      .mem_axi4_0_awaddr       (io_axi4_0_awaddr),
      .mem_axi4_0_awlen        (io_axi4_0_awlen),
      .mem_axi4_0_awsize       (io_axi4_0_awsize),
      .mem_axi4_0_awburst      (io_axi4_0_awburst),
      .mem_axi4_0_wready       (io_axi4_0_wready),
      .mem_axi4_0_wvalid       (io_axi4_0_wvalid),
      .mem_axi4_0_wdata        (io_axi4_0_wdata),
      .mem_axi4_0_wstrb        (io_axi4_0_wstrb),
      .mem_axi4_0_wlast        (io_axi4_0_wlast),
      .mem_axi4_0_bready       (io_axi4_0_bready),
      .mem_axi4_0_bvalid       (io_axi4_0_bvalid),
      .mem_axi4_0_bid          (io_axi4_0_bid),
      .mem_axi4_0_bresp        (io_axi4_0_bresp),
      .mem_axi4_0_arready      (io_axi4_0_arready),
      .mem_axi4_0_arvalid      (io_axi4_0_arvalid),
      .mem_axi4_0_arid         (io_axi4_0_arid),
      .mem_axi4_0_araddr       (io_axi4_0_araddr),
      .mem_axi4_0_arlen        (io_axi4_0_arlen),
      .mem_axi4_0_arsize       (io_axi4_0_arsize),
      .mem_axi4_0_arburst      (io_axi4_0_arburst),
      .mem_axi4_0_rready       (io_axi4_0_rready),
      .mem_axi4_0_rvalid       (io_axi4_0_rvalid),
      .mem_axi4_0_rid          (io_axi4_0_rid),
      .mem_axi4_0_rdata        (io_axi4_0_rdata),
      .mem_axi4_0_rresp        (io_axi4_0_rresp),
      .mem_axi4_0_rlast        (io_axi4_0_rlast),
      //dma
      .slave_axi4_mem_0_awready(),
      .slave_axi4_mem_0_awvalid(1'b0),
      .slave_axi4_mem_0_awid   (4'b0),
      .slave_axi4_mem_0_awaddr (32'b0),
      .slave_axi4_mem_0_awlen  (8'b0),
      .slave_axi4_mem_0_awsize (3'b0),
      .slave_axi4_mem_0_awburst(2'b0),
      .slave_axi4_mem_0_wready (),
      .slave_axi4_mem_0_wvalid (1'b0),
      .slave_axi4_mem_0_wdata  (64'b0),
      .slave_axi4_mem_0_wstrb  (8'b0),
      .slave_axi4_mem_0_wlast  (1'b0),
      .slave_axi4_mem_0_bready (1'b0),
      .slave_axi4_mem_0_bvalid (),
      .slave_axi4_mem_0_bid    (),
      .slave_axi4_mem_0_bresp  (),
      .slave_axi4_mem_0_arready(),
      .slave_axi4_mem_0_arvalid(1'b0),
      .slave_axi4_mem_0_arid   (4'b0),
      .slave_axi4_mem_0_araddr (32'b0),
      .slave_axi4_mem_0_arlen  (8'b0),
      .slave_axi4_mem_0_arsize (3'b0),
      .slave_axi4_mem_0_arburst(2'b0),
      .slave_axi4_mem_0_rready (1'b0),
      .slave_axi4_mem_0_rvalid (),
      .slave_axi4_mem_0_rid    (),
      .slave_axi4_mem_0_rdata  (),
      .slave_axi4_mem_0_rresp  (),
      .slave_axi4_mem_0_rlast  ()
  );

  SimAXIMem u_old_ip_chiplink_SimAXIMem (
      .clock            (osc_clk_25m_i_pad),
      .reset            (~ext_rst_n_i_pad),
      .io_axi4_0_awready(io_axi4_0_awready),
      .io_axi4_0_awvalid(io_axi4_0_awvalid),
      .io_axi4_0_awid   (io_axi4_0_awid),
      .io_axi4_0_awaddr (io_axi4_0_awaddr[30:0]),
      .io_axi4_0_awlen  (io_axi4_0_awlen),
      .io_axi4_0_awsize (io_axi4_0_awsize),
      .io_axi4_0_awburst(io_axi4_0_awburst),
      .io_axi4_0_wready (io_axi4_0_wready),
      .io_axi4_0_wvalid (io_axi4_0_wvalid),
      .io_axi4_0_wdata  (io_axi4_0_wdata),
      .io_axi4_0_wstrb  (io_axi4_0_wstrb),
      .io_axi4_0_wlast  (io_axi4_0_wlast),
      .io_axi4_0_bready (io_axi4_0_bready),
      .io_axi4_0_bvalid (io_axi4_0_bvalid),
      .io_axi4_0_bid    (io_axi4_0_bid),
      .io_axi4_0_bresp  (io_axi4_0_bresp),
      .io_axi4_0_arready(io_axi4_0_arready),
      .io_axi4_0_arvalid(io_axi4_0_arvalid),
      .io_axi4_0_arid   (io_axi4_0_arid),
      .io_axi4_0_araddr (io_axi4_0_araddr[30:0]),
      .io_axi4_0_arlen  (io_axi4_0_arlen),
      .io_axi4_0_arsize (io_axi4_0_arsize),
      .io_axi4_0_arburst(io_axi4_0_arburst),
      .io_axi4_0_rready (io_axi4_0_rready),
      .io_axi4_0_rvalid (io_axi4_0_rvalid),
      .io_axi4_0_rid    (io_axi4_0_rid),
      .io_axi4_0_rdata  (io_axi4_0_rdata),
      .io_axi4_0_rresp  (io_axi4_0_rresp),
      .io_axi4_0_rlast  (io_axi4_0_rlast)
  );

  sdr u_old_ip_sdram_sdr (
      .Dq   (old_ip_sdram_data_io_pad),
      .Addr (old_ip_sdram_addr_o_pad),
      .Ba   (old_ip_sdram_ba_o_pad),
      .Clk  (old_ip_sdram_clk_o_pad),
      .Cke  (old_ip_sdram_cke_o_pad),
      .Cs_n (old_ip_sdram_cs_o_pad),
      .Ras_n(old_ip_sdram_ras_o_pad),
      .Cas_n(old_ip_sdram_cas_o_pad),
      .We_n (old_ip_sdram_we_o_pad),
      .Dqm  (old_ip_sdram_dqm_o_pad)
  );


  initial begin
    osc_clk_25m_i = 1'b0;
    forever begin
      #(OSC_CLK_25M_PEROID / 2) osc_clk_25m_i <= ~osc_clk_25m_i;
    end
  end

  initial begin
    osc_clk_12288k_i = 1'b0;
    forever begin
      #(OSC_CLK_12288K_PEROID / 2) osc_clk_12288k_i <= ~osc_clk_12288k_i;
    end
  end

  initial begin
    rcu0_pll_en_i = 1'b1;  // en pll
    if ($test$plusargs("cfg_0"))  // 100M
      rcu0_clk_cfg_i = 3'd0;
    else if ($test$plusargs("cfg_1"))  // 200M
      rcu0_clk_cfg_i = 3'd1;
    else if ($test$plusargs("cfg_2"))  // 300M
      rcu0_clk_cfg_i = 3'd2;
    else if ($test$plusargs("cfg_3"))  // 400M
      rcu0_clk_cfg_i = 3'd3;
    else if ($test$plusargs("cfg_4"))  // 500M
      rcu0_clk_cfg_i = 3'd4;
    else if ($test$plusargs("cfg_5"))  // 600M
      rcu0_clk_cfg_i = 3'd5;
    else if ($test$plusargs("cfg_6"))  // 700M
      rcu0_clk_cfg_i = 3'd6;
    else if ($test$plusargs("cfg_7"))  // 800M
      rcu0_clk_cfg_i = 3'd7;
    else rcu0_clk_cfg_i = 3'd0;  // 100M
    $display("rcu0_clk_cfg_i = %b", rcu0_clk_cfg_i);

    sim_reset(40);  // reset
    // while (1) begin
    //   for (integer i = 8'h1C; i < 8'hFF; i++) begin
    //     u_ps20_kdb_model.send_code(i);
    //   end
    // end
  end

  initial begin
    $fsdbDumpfile("asic_top.fsdb");
    $fsdbDumpvars(0);
    #10000000; $finish;
  end

endmodule

